SÁNDOR MÁTHÉ

I am a passionate FPGA engineer and architect. This technology accompanied my full professional career. Even though I have more then a decade of experience in this field in various, mostly signal processing related projects, I am still fascinated the freedom and power it gives to designers.

• English: fluent
  
• Hungarian: native speaker

Battery charger controller: 20 channel, model based control system for battery charging / depleting using Kria SOM

• Target language: Verilog / VHDL mixed language project
• Main tasks: architecture design, interfacing to battery management IC, charge process control implementation, UI and Ethernet communication implementation, simulation environment
• Project duration: 6 months

SW radio project with Kintex 7 FPGA: design and implementation of 16 Ch DDC and DUC, USB3 streaming interface with synchronous FIFO interface

• Target language: Verilog / VHDL mixed language project
• Main tasks: architecture design, algorithm modeling in Matlab, implementation using Xilinx and custom IP, PC tool for data collection and spectral analysis, ADC and DAC interfacing, self-checking simulator environment development
• Project duration: 2 years

Accelerometer signal processing:  3 channel signal processing system for satellite module's accelerometer sensor

• Target language: VHDL
• Main tasks: architecture design, algorithm integration, implementation using custom IP, ADC interfacing, self-checking simulator environment development
• Project duration: 1 year

Video bridging application with Lattice Crosslink family: feasibility study to replace long-lead ASIC with Lattice Crosslink FPGA

• Target language: Verilog
• Main tasks: evaluation and setup of early prototype based on Lattice sample project, project adaptation to customer specific video settings
• Project duration: 6 months

FPGA testing firmware for chip recycling with Kintex 7 platform: IO, GTX transciever and BRAM testing

• Target language: VHDL
• Main tasks: architecture design, constraints generation based on schematic, PC tool for result evaluation
• Project duration: 6 months

Internal tool development: simulator environment for efficient signal and data stream analysis using Matlab

• Main tasks: interfacing Vivado and Questa simulators with Matlab to allow capture and analysis simulation results directly in Matlab workspace
• Project duration: 3-6 months

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